On Mon, May 14, 2018 at 6:41 PM, Lucas Stach [off-list ref] wrote:

Am Montag, den 14.05.2018, 17:42 +0530 schrieb Pintu Kumar:

quoted

Hi,

Is there any work around possible to set IRQ affinity for some GPIO
interrupt ?
How to avoid CPU0 to receive the current GPIO interrupt ?
How do we assign GPIO interrupts to any CPU other than CPU0 ?
Is it possible to isolate CPU0 for a sometime, from my GPIO driver so
that GPIO interrupt can be served by another CPU ?

Need your inputs to decide whether it is still possible to set
affinity for GPIO interrupt, or its impossible ?

This is not possible. The GPIO IRQs are aggregated into one GPC/GIC IRQ
line per GPIO bank, so it is not possible to change affinity of a
single GPIO interrupt to another CPU.

OK. Thanks for your confirmation.

Best we could do is change the
affinity of the whole bank,

OK. How can we do this on the fly from my driver code.
If you have any reference please let me know.
This is required only for experimental purpose to prove the point to be mgmt.
My idea is, from the driver, change the affinity of the whole bank.
So, the GPIO interrupt can be delivered on to this specific CPU bank.
Once I am done, I will revert back to the old bank.
Please give me some hint on how to do this from my kernel module....

but given the limited usefulness of
something like that, nobody bothered to implement such a thing.

Regards,
Lucas

quoted

On Fri, May 11, 2018 at 8:07 PM, Pintu Kumar [off-list ref]
wrote:

quoted

On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.d
e> wrote:

quoted

Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King -
ARM Linux:

quoted

On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote:

quoted

Hi,

I need one help.
I am using i.MX7 Sabre board with kernel version 4.1.15

Let's say I am interested in GPIO number: 21
I wanted to set CPU affinity for particular GPIO->IRQ number,
so I
tried the below steps:
root at 10:~# echo 21 > /sys/class/gpio/export
root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge
root at 10:~# cat /proc/interrupts | grep 21
  47: 0 0 gpio-mxc 21 Edge gpiolib
root at 10:~# cat /sys/class/gpio/gpio21/direction
in
root at 10:~# cat /proc/irq/47/smp_affinity
3
root at 10:~# echo 2 > /proc/irq/47/smp_affinity
-bash: echo: write error: Input/output error

But I get input/output error.
When I debug further, found that irq_can_set_affinity is
returning 0:
[    0.000000] genirq: irq_can_set_affinity (0): balance: 1,
irq_data.chip: a81b7e48, irq_set_affinity:   (null)
[    0.000000] write_irq_affinity: FAIL

I also tried first setting /proc/irq/default_smp_affinity to
2 (from 3).
This change is working, but the smp_affinity setting for the
new IRQ
is not working.

When I try to set smp_affinity for mmc0, then it works.
# cat /proc/interrupts | grep mmc
295:         55          0     GPCV2  22 Edge      mmc0
296:          0          0     GPCV2  23 Edge      mmc1
297:         52          0     GPCV2  24 Edge      mmc2

root at 10:~# echo 2 > /proc/irq/295/smp_affinity
root at 10:~#


So, I wanted to know what are the conditions for which
setting
smp_affinity for an IRQ will work ?

Is there any way by which I can set CPU affinity to a GPIO ->
IRQ ?
Whether, irq_set_affinity_hint() will work in this case ?

IRQ affinity is only supported where interrupts are _directly_
wired to
the GIC.  It's the GIC which does the interrupt steering to the
CPU
cores.

Interrupts on downstream interrupt controllers (such as GPCV2)
have no
ability to be directed independently to other CPUs - the only
possible
way to change the mapping is to move _all_ interrupts on that
controller,
and any downstream chained interrupts at GIC level.

Hence why Interrupt 295 has no irq_set_affinity function: there
is no way
for the interrupt controller itself to change the affinity of
the input
interrupt.

The GPCv2 though is a secondary IRQ controller which has a 1:1
mapping
of its input IRQs to the upstream GIC IRQ lines. Affinity can
thus be
handled by forwarding the request to the GIC by
irq_chip_set_affinity_parent().

As this is handled correctly in the upstream kernel since the
first
commit introducing support for the GPCv2, it seems the issue is
only
present in some downstream kernel.

OK. Thanks so much for your reply.

I saw some of the drivers using irq_set_affinity_hint() to force
the
IRQ affinity to a particular CPU.
This is the sample:
{
cpumask_clear(mask);
cpumask_set_cpu(cpu, mask);
irq_set_affinity_hint(irq, mask);
}

Whether this logic will work for a particular GPIO pin ?

quoted

Regards,
Lucas