[PATCH 2/2] pinctrl: nand: meson-gxl: fix missing data pins
From: Yixun Lan <hidden>
Date: 2018-05-09 14:10:32
Also in:
linux-amlogic, linux-gpio, lkml
Subsystem:
arm/amlogic meson soc support, pin control subsystem, the rest · Maintainers:
Neil Armstrong, Kevin Hilman, Linus Walleij, Linus Torvalds
The data pin 0-7 of the NAND controller are actually missing from
the nand pinctrl group, so we fix it here.
Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
Reported-by: Liang Yang <liang.yang@amlogic.com>
Signed-off-by: Yixun Lan <redacted>
---
drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index b3786cde963d..7dae1d7bf6b0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c@@ -617,8 +617,8 @@ static const char * const sdio_groups[] = { }; static const char * const nand_groups[] = { - "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle", - "nand_wen_clk", "nand_ren_wr", "nand_dqs", + "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", + "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs", }; static const char * const uart_a_groups[] = {
--
2.17.0