Sekhar,

On 04/27/2018 09:05 AM, Rob Herring wrote:

On Thu, Apr 26, 2018 at 07:17:42PM -0500, David Lechner wrote:

quoted

This adds new device tree bindings for the timer IP block of TI
DaVinci-like SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
---

v9 changes:
- new patch in v9


  .../bindings/timer/ti,davinci-timer.txt       | 24 +++++++++++++++++++
  1 file changed, 24 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/timer/ti,davinci-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt
new file mode 100644
index 000000000000..2091eca46981
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt

@@ -0,0 +1,24 @@
+* Device tree bindings for Texas Instruments DaVinci timer
+
+This document provides bindings for the 64-bit timer in the DaVinci
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+It is global timer is a free running up-counter and can generate interrupt

Doesn't make sense, too many 'is'.

There's no interrupt property listed.

quoted

+when the counter reaches preset counter values.
+
+Required properties:
+
+- compatible : should be "ti,davinci-timer".
+- reg : specifies base physical address and count of the registers.
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+	clocksource: timer at 20000 {
+		compatible = "ti,davinci-timer";
+		reg = <0x20000 0x1000>;
+		clocks = <&pll0_auxclk>;
+	};
-- 
2.17.0

What do you think about trying to reuse the keystone timer here instead of
introducing our own binding? I assume it is basically the same since the
watchdog timer is shared already between davinci and keystone.