? 2018?3?27? GMT+08:00 ??6:22:58, Rob Herring [off-list ref] ??:

On Thu, Mar 22, 2018 at 02:08:43PM +0800, Icenowy Zheng wrote:

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? 2018?3?22? GMT+08:00 ??1:13:42, "Jernej ?krabec"

[off-list ref] ??:

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Hi all,

Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng

napisal(a):

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? 2018?3?21? GMT+08:00 ??2:46:46, Maxime Ripard

[off-list ref] 
??:

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On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:

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All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64

SoC

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to

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be claimed, otherwise the whole DE2 space is inaccessible.

Add a device tree binding of the DE2 part as a sub-bus.

Where did you get the info that it was a bus?

There's no direct evidence, just some guess.

The DE2 is a whole part that is just allocated a memory
space at the user manual, and the SRAM controls the
access to all modules in the DE2.

So it might be a bus.

Implement it as a bus is a clear representation on A64.

Since there is already syscon for same mmio region, we migh as well

use

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it 
when loading ccu-sun8i-de2 driver on A64.

Other options, like SRAM driver or bus driver, might better

represent

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HW, but 

I think the device tree should properly represent the HW,
it's a basic requirment.

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then we would have two DT nodes covering same mmio region, which I
think is 
not really acceptable.

It's acceptable, and DE2 is not the only user of SRAM controller so

far.

No, it's not acceptable. Don't create overlapping mmio regions in DT.

Then should the SRAM controller driver be configured to take the syscon?

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VE will also need a SRAM region to be claimed.

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Any suggestions?

BTW, H6 has same design in this regard.

Best regards,
Jernej

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