[PATCH v4 6/7] scsi: bnx2i: Eliminate duplicate barriers on weakly-ordered archs
From: Sinan Kaya <hidden>
Date: 2018-03-20 02:50:37
Also in:
linux-arm-msm, linux-scsi, lkml
Subsystem:
broadcom bnx2i 1/10 gigabit iscsi driver, scsi subsystem, the rest · Maintainers:
Nilesh Javali, Manish Rangankar, "James E.J. Bottomley", "Martin K. Petersen", Linus Torvalds
Code includes barrier() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya <redacted> --- drivers/scsi/bnx2i/bnx2i_hwi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/bnx2i/bnx2i_hwi.c b/drivers/scsi/bnx2i/bnx2i_hwi.c
index 8f03a86..075735b 100644
--- a/drivers/scsi/bnx2i/bnx2i_hwi.c
+++ b/drivers/scsi/bnx2i/bnx2i_hwi.c@@ -278,7 +278,7 @@ static void bnx2i_ring_sq_dbell(struct bnx2i_conn *bnx2i_conn, int count) sq_db->prod_idx = ep->qp.sq_prod_idx; bnx2i_ring_577xx_doorbell(bnx2i_conn); } else - writew(count, ep->qp.ctx_base + CNIC_SEND_DOORBELL); + writew_relaxed(count, ep->qp.ctx_base + CNIC_SEND_DOORBELL); mmiowb(); /* flush posted PCI writes */ }
--
2.7.4