Thread (12 messages) 12 messages, 5 authors, 2018-02-16

[PATCH v9 2/3] arm: dts: add Nuvoton NPCM750 device tree

From: joel@jms.id.au (Joel Stanley)
Date: 2018-02-13 06:23:25
Also in: linux-devicetree, lkml, openbmc

Hi Brendan,

On Tue, Feb 6, 2018 at 10:27 AM, Brendan Higgins
[off-list ref] wrote:
Add a common device tree for all Nuvoton NPCM750 BMCs and a board
specific device tree for the NPCM750 (Poleg) evaluation board.

Signed-off-by: Brendan Higgins <redacted>
Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Avi Fishman <avifishman70@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Tomer Maimon <tmaimon77@gmail.com>
Tested-by: Avi Fishman <avifishman70@gmail.com>
This looks well acked, reviewed and tested. How do you plan to have
the ARM SoC maintainers merge your patches?
---
 .../arm/cpu-enable-method/nuvoton,npcm7xx-smp      |  42 ++++++
 .../devicetree/bindings/arm/npcm/npcm.txt          |   6 +
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts          |  35 +++++
 arch/arm/boot/dts/nuvoton-npcm750.dtsi             | 162 +++++++++++++++++++++
 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h   |  35 +++++
 5 files changed, 280 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp
 create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
You need to add nuvoton-npcm750-evb.dts to arch/arm/boot/dts/Makefile

Once you've done that you can add

Tested-by: Joel Stanley <joel@jms.id.au>

as I tested this on an EVB.
quoted hunk ↗ jump to hunk
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..08e906f88c49
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "nuvoton,npcm7xx-smp";
+
+               cpu at 0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       clocks = <&clk NPCM7XX_CLK_CPU>;
+                       clock-names = "clk_cpu";
+                       reg = <0>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu at 1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       clocks = <&clk NPCM7XX_CLK_CPU>;
+                       clock-names = "clk_cpu";
+                       reg = <1>;
+                       next-level-cache = <&l2>;
+               };
+       };
+
+/* external clock signal rg1refck, supplied by the phy */
+clk-rg1refck {
+       compatible = "fixed-clock";
+       #clock-cells = <0>;
+       clock-frequency = <125000000>;
+};
+
+/* external clock signal rg2refck, supplied by the phy */
+clk-rg2refck {
+       compatible = "fixed-clock";
+       #clock-cells = <0>;
+       clock-frequency = <125000000>;
+};
+
+clk-xin {
+       compatible = "fixed-clock";
+       #clock-cells = <0>;
+       clock-frequency = <50000000>;
+};
The whitespace here needs to be fixed.

Cheers,

Joel
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+               ranges = <0x0 0xf0000000 0x00900000>;
+
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