On Thu, Feb 01, 2018 at 05:09:33PM +0100, Giulio Benetti wrote:

Il 01/02/2018 11:14, Maxime Ripard ha scritto:

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On Sat, Jan 27, 2018 at 11:07:09PM +0100, Giulio Benetti wrote:

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I don't really know what the polarity of D0 would be just by
judging at that capture, but we would have noticed if the colors
were inverted for quite some time now.

D0-D23 are correct.

With that capture, I mean to show you instead dclk is inverted, as
dclk samples D0 on falling edge.

Ah right, DCLK being the first channel?

Yes, sorry I didn't place a label on channels

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So 0 is NEGEDGE and 1 is POSEDGE(1/3 of clock phase).
1/3 clock phase seems enough to me to be considered POSEDGE,
2/3 instead risks to go too much to the right of D0(even if it
could work).

Do you have captures with both settings?

Not now, but asap I'm going to take.

Here we are:
1/3 phase: https://pasteboard.co/H4VehON.png
2/3 phase: https://pasteboard.co/H4Veq8a.png

Yellow: D0
Blue: DCLK

As you can see:
1/3 phase has DCLK rising edge almost in the middle of D0
2/3 phase has DCLK rising edge that comes too late

I would go for "1/3 phase" for Rising edge and "normal phase" for
Falling edge.

What do you think?

It seems fair. This need a whole lot of comments though :)

Yes, then, do I proceed resubmitting both corrected patches with corrected
commit logs?

Yes, please.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
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