On Monday, October 9, 2017 10:44 AM, Krzysztof Kozlowski wrote:

On Mon, Oct 9, 2017 at 4:14 PM, Pankaj Dubey [off-list ref]
wrote:

quoted

From: Anvesh Salveru <redacted>

In exynos_pcie_establish_link if driver is not using generic phy,
we are resetting PHY twice, which is redundant, so this patch removes

Hi Pankaj,

This lacks the information why it is redundant.

(I resend this mail, because email address of pci list was corrupted.)

I think so, too.

Did you test this code on some boards with Exynos PCIe?
Or did hardware engineers confirm this?
Please add more information on this patch.

Best regards,
Jingoo Han

quoted

repeated lines of code for PHY reset.

Signed-off-by: Anvesh Salveru <redacted>

Your Signed-off-by is needed here.

Best regards,
Krzysztof

quoted

---
 drivers/pci/dwc/pci-exynos.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 5596fde..85d2f4b 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c

@@ -423,13 +423,6 @@ static int exynos_pcie_establish_link(struct

exynos_pcie *ep)

quoted

                exynos_pcie_deassert_phy_reset(ep);
                exynos_pcie_power_on_phy(ep);
                exynos_pcie_init_phy(ep);
-
-               /* pulse for common reset */
-               exynos_pcie_writel(ep->mem_res->block_base, 1,
-                                       PCIE_PHY_COMMON_RESET);
-               udelay(500);
-               exynos_pcie_writel(ep->mem_res->block_base, 0,
-                                       PCIE_PHY_COMMON_RESET);
        }

        /* pulse for common reset */
--
2.7.4