On Wed, Sep 27, 2017 at 02:32:37PM +0100, Shameer Kolothum wrote:

From: John Garry <redacted>

The HiSilicon erratum 161010801 describes the limitation of HiSilicon
platforms hip06/hip07 to support the SMMU mappings for MSI transactions.

On these platforms, GICv3 ITS translator is presented with the deviceID
by extending the MSI payload data to 64 bits to include the deviceID.
Hence, the PCIe controller on this platforms has to differentiate the MSI
payload against other DMA payload and has to modify the MSI payload.
This basically makes it difficult for this platforms to have a SMMU
translation for MSI.

This patch adds a compatible string to implement this errata for
HiSilicon Hi161x SMMUv3 model on hip06/hip07 platforms.

Also, the arm64 silicon errata is updated with this same erratum.

Signed-off-by: John Garry <redacted>
[Shameer: Modified to use compatible string for errata]
Signed-off-by: Shameer Kolothum <redacted>
---
 Documentation/arm64/silicon-errata.txt                  | 1 +
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>