Thread (8 messages) 8 messages, 3 authors, 2017-09-19

[PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801

From: Shameerali Kolothum Thodi <hidden>
Date: 2017-09-19 16:09:33
Also in: linux-acpi, linux-devicetree, linux-iommu

-----Original Message-----
From: Rob Herring [mailto:robh at kernel.org]
Sent: Tuesday, September 19, 2017 3:53 PM
To: Shameerali Kolothum Thodi <redacted>
Cc: lorenzo.pieralisi at arm.com; marc.zyngier at arm.com;
sudeep.holla at arm.com; will.deacon at arm.com; robin.murphy at arm.com;
joro at 8bytes.org; mark.rutland at arm.com; hanjun.guo at linaro.org; Gabriele
Paoloni [off-list ref]; John Garry
[off-list ref]; iommu at lists.linux-foundation.org; linux-arm-
kernel at lists.infradead.org; linux-acpi at vger.kernel.org;
devicetree at vger.kernel.org; devel at acpica.org; Linuxarm
[off-list ref]; Wangzhou (B) [off-list ref];
Guohanjun (Hanjun Guo) [off-list ref]
Subject: Re: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for
HiSilicon erratum 161010801

On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:
quoted
From: John Garry <redacted>

The HiSilicon erratum 161010801 describes the limitation of HiSilicon
platforms
quoted
hip06/hip07 to support the SMMU mappings for MSI transactions.

On these platforms, GICv3 ITS translator is presented with the deviceID
by extending the MSI payload data to 64 bits to include the deviceID.
Hence, the PCIe controller on this platforms has to differentiate the MSI
payload against other DMA payload and has to modify the MSI payload.
This basically makes it difficult for this platforms to have a SMMU
translation for MSI.

This patch adds a SMMUv3 binding to flag that the SMMU breaks msi
translation at ITS.

Also, the arm64 silicon errata is updated with this same erratum.

Signed-off-by: John Garry <redacted>
Signed-off-by: Shameer Kolothum
[off-list ref]
[...]
quoted
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
@@ -55,6 +55,9 @@ the PCIe specification.
 - hisilicon,broken-prefetch-cmd
                     : Avoid sending CMD_PREFETCH_* commands to the SMMU.

+- hisilicon,broken-untranslated-msi
+                    : Reserve ITS HW region to avoid translating msi.
+
This should be determined from the compatible string. Continuing to add
properties for each errata doesn't scale.
Ok. I think the suggestion here is to follow the arm-smmu.c (SMMUv1/v2) 
driver way of implementing the errata. As you might have noticed,  the 
SMMUv3 driver dt errata framework depends on properties  and this will
change the way errata is implemented in the driver now.

Hi Will/Robin,
Could you please take a look and let us know your thoughts on changing
the SMMUv3 dt errata implementation to version/model/compatible string
framework for this quirk.

Thanks,
Shameer
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help