[PATCH 00/26] coresight: next v4.13-rc3 · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 01/26] coresight: Correct buffer lost increment · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 02/26] coresight: etb10: Remove useless conversion to LE · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 03/26] coresight: Add barrier packet for synchronisation · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 04/26] coresight: etb10: Move etb_disable_hw() outside of lock · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 05/26] coresight: etm3x: Set synchronisation frequencty to TRM default · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 06/26] hwtracing: coresight: constify attribute_group structures. · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 07/26] coresight: pmu: Adds return stack option to perf coresight pmu · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 08/26] coresight: ptm: Adds trace return stack option programming for PTM. · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 09/26] coresight: etm4x: Adds trace return stack option programming for ETMv4. · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 10/26] coresight replicator: Cleanup programmable replicator naming · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 11/26] coresight: Add support for reading 64bit registers · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 12/26] coresight: Use the new helper for defining registers · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 13/26] coresight tmc: Add helpers for accessing 64bit registers · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 14/26] coresight tmc: Expose DBA and AXICTL · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 15/26] coresight replicator: Expose replicator management registers · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 16/26] coresight tmc: Handle configuration types properly · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 17/26] coresight tmc etr: Add capabilitiy information · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 18/26] coresight tmc: Detect support for scatter gather · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 19/26] coresight tmc etr: Detect address width at runtime · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 20/26] coresight tmc etr: Cleanup AXICTL register handling · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 21/26] coresight tmc etr: Setup AXI cache encoding for read transfers · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 22/26] coresight tmc: Support for save-restore in ETR · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 23/26] coresight tmc: Add support for Coresight SoC 600 TMC · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 24/26] coresight: Add support for Coresight SoC 600 components · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 25/26] perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 26/26] coresight: STM: Clean up __iomem type usage · mathieu.poirier@linaro.org (Mathieu Poirier) · 2017-08-02
[PATCH 00/26] coresight: next v4.13-rc3 · gregkh@linuxfoundation.org (Greg KH) · 2017-08-28

STALE3289d

[PATCH 16/26] coresight tmc: Handle configuration types properly

From: mathieu.poirier@linaro.org (Mathieu Poirier)
Date: 2017-08-02 16:22:10
Subsystem: arm/coresight framework and drivers, hardware tracing facilities, the rest · Maintainers: Suzuki K Poulose, Alexander Shishkin, Linus Torvalds

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. This would break
the existing driver which will treat anything other than ETR/ETB as an
ETF. Fix the driver to check the configuration type properly and also
add a warning if we encounter an unsupported configuration (ETS).

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index bd98b5101528..6adf74689a85 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c

@@ -360,11 +360,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 	desc.dev = dev;
 	desc.groups = coresight_tmc_groups;
 
-	if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
+	switch (drvdata->config_type) {
+	case TMC_CONFIG_TYPE_ETB:
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etb_cs_ops;
-	} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
+		break;
+	case TMC_CONFIG_TYPE_ETR:
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etr_cs_ops;

@@ -375,10 +377,16 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 		if (ret)
 			goto out;
-	} else {
+		break;
+	case TMC_CONFIG_TYPE_ETF:
 		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 		desc.ops = &tmc_etf_cs_ops;
+		break;
+	default:
+		pr_err("%s: Unsupported TMC config\n", pdata->name);
+		ret = -EINVAL;
+		goto out;
 	}
 
 	drvdata->csdev = coresight_register(&desc);

-- 
2.7.4