[linux-sunxi] Re: [PATCH v6 1/6] clk: sunxi-ng: div: Add support for fixed post-divider
From: icenowy@aosc.io (icenowy at aosc.io)
Date: 2017-08-12 04:49:50
Also in:
linux-clk, linux-devicetree, lkml
? 2017-08-12 12:13?Chen-Yu Tsai ???
On Sat, Aug 12, 2017 at 11:07 AM, [off-list ref] wrote:quoted
? 2017-07-17 16:52?Maxime Ripard ???quoted
On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote:quoted
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes <redacted> --- drivers/clk/sunxi-ng/ccu_div.c | 15 +++++++++++++-- drivers/clk/sunxi-ng/ccu_div.h | 3 ++- 2 files changed, 15 insertions(+), 3 deletions(-)diff --git a/drivers/clk/sunxi-ng/ccu_div.cb/drivers/clk/sunxi-ng/ccu_div.c index c0e5c10..744502a 100644--- a/drivers/clk/sunxi-ng/ccu_div.c +++ b/drivers/clk/sunxi-ng/ccu_div.c@@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(structccu_mux_internal *mux, { struct ccu_div *cd = data; + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate *= cd->fixed_post_div; + return divider_round_rate_parent(&cd->common.hw, parent, rate, parent_rate, cd->div.table, cd->div.width,You still haven't addressed the biggest issue with this patch, see: https://patchwork.kernel.org/patch/9825565/I think he has already did the changes suggested in the review.Nope. Only half of it is fixed. First you "unapply" the post-divider, i.e. multiply the rate by the divider. Then you pass it to divider_round_rate_parent. You still have to reapply the divider to the result. This last part is missing. This means the clock rate returned by ccu_div_round_rate is going to be off. Instead the return statement should be return divider_round_rate_parent(...) / cd->fixed_post_div
Oh, got it by reading other CCU clock types that has fixed postdiv. Thanks!
ChenYuquoted
(P.S. during developing R40 CCU driver I found that pll-periph0-sata also needs this patch, so I'm rechecking it)quoted
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