[PATCH v2 06/23] clk: rockchip: support more clks for rv1108

Hi Andy,

Am Mittwoch, 2. August 2017, 16:33:57 CEST schrieb Andy Yan:

From: Elaine Zhang <redacted>

Added the description of the missing clock,
make the clock tree more complete.

Signed-off-by: Elaine Zhang <redacted>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

[...]

 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 
-	COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
+	/* PD_BUS */
+	GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
+			RV1108_CLKGATE_CON(1), 0, GFLAGS),
+	GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
+			RV1108_CLKGATE_CON(1), 1, GFLAGS),
+	GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
+			RV1108_CLKGATE_CON(1), 2, GFLAGS),
+	COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
+			RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
+	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
+			RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
+			RV1108_CLKGATE_CON(1), 4, GFLAGS),

you're adding a (new / second) hclk_bus_pre here, but only drop the
old in patch 7. Please structure patch-contents in a way that each patch
is self-contained and works on its own ... aka the clock tree should not
get worse if only patch 6 is applied (like in a random git bisect), but
here the state is bad between these 2 patches.

hclk_bus_pre also is only _one_ example and there are probably more of
those hiding in these clock patches. So please fix these issues.


Thanks
Heiko