On Mon, Jul 31, 2017 at 8:21 AM, Masahiro Yamada
[off-list ref] wrote:

For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers.  So, the register offset must be
taken into account.  Otherwise, wrong input-enable status is displayed.

While we here, rename the macro because it is a base address.

Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs")
Signed-off-by: Masahiro Yamada <redacted>

Patch applied.

Yours,
Linus Walleij