cpufreq: frequency scaling spec in DT node
From: viresh.kumar@linaro.org (Viresh Kumar)
Date: 2017-07-12 10:09:42
Also in:
linux-pm
From: viresh.kumar@linaro.org (Viresh Kumar)
Date: 2017-07-12 10:09:42
Also in:
linux-pm
On 12-07-17, 11:58, Mason wrote:
I would object to the characterization of "just a PLL" :-) The PLL outputs "garbage" before actually "locking" a target frequency. It is not possible for the CPU to blindly change the PLL settings, because that crashes the system. The bootloader implements the steps required to change said settings, so the strategy has been: have Linux use whatever PLL frequency the bootloader programs. Behind the PLL, there is a glitch-free divider, which is able to divide the PLL output without crashing the system. I've been using that divider for DFS. drivers/clk/clk-tango4.c
Okay, got it now. Yes, you *really* need to create these OPPs dynamically. I am convinced now :) -- viresh