Thread (30 messages) 30 messages, 5 authors, 2017-07-27

[PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers

From: Suzuki.Poulose@arm.com (Suzuki K Poulose)
Date: 2017-07-25 09:29:35
Also in: lkml

On 24/07/17 18:11, Mathieu Poirier wrote:
On 20 July 2017 at 04:17, Suzuki K Poulose [off-list ref] wrote:
quoted
Coresight TMC splits 64bit registers into a pair of 32bit registers
(e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 51c0185..c78de00 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -18,6 +18,7 @@
 #ifndef _CORESIGHT_TMC_H
 #define _CORESIGHT_TMC_H

+#include <linux/io.h>
Is this needed?  I recompiled on my side without it and nothing breaks.
I think it is a left over from rebase, where I initially open coded the
read/write_relaxed here and then later moved to the coresight-priv.h. So,
yes, please could you fix it up when you commit ?

Cheers
Suzuki
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help