[linux-sunxi] [RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE
From: icenowy@aosc.io (Icenowy Zheng)
Date: 2017-05-24 05:37:08
Also in:
dri-devel, linux-clk, linux-devicetree, lkml
? 2017?5?24? GMT+08:00 ??1:34:58, Chen-Yu Tsai [off-list ref] ??:
On Wed, May 24, 2017 at 1:28 PM, Icenowy Zheng [off-list ref] wrote:quoted
? 2017?5?24? GMT+08:00 ??1:24:29, Chen-Yu Tsai [off-list ref] ??:quoted
On Thu, May 18, 2017 at 12:43 AM, Icenowy Zheng [off-list ref] wrote:quoted
As we have already the support for the TV encoder on Allwinner H3,addquoted
the display engine pipeline device tree nodes to its DTSI file. The H5 pipeline has some differences and will be enabled later. The currently-unused mixer0 and tcon0 are also needed, for the completement of the pipeline. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 189++++++++++++++++++++++++++++++++++++++++quoted
1 file changed, 189 insertions(+)diff --git a/arch/arm/boot/dts/sun8i-h3.dtsib/arch/arm/boot/dts/sun8i-h3.dtsiquoted
index b36f9f423c39..20172ef92415 100644--- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi@@ -41,6 +41,8 @@ */ #include "sunxi-h3-h5.dtsi" +#include <dt-bindings/clock/sun8i-de2.h> +#include <dt-bindings/reset/sun8i-de2.h> / { cpus {@@ -72,6 +74,193 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-h3-display-engine"; + allwinner,pipelines = <&mixer0>, + <&mixer1>; + status = "disabled"; + }; + + soc { + display_clocks: clock at 1000000 { + compatible ="allwinner,sun8i-a83t-de2-clk";quoted
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+ reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&ccu CLK_DE>; + assigned-clock-parents = <&ccu CLK_PLL_DE>; + assigned-clock-rates = <432000000>; + }; + + mixer0: mixer at 1100000 { + compatible ="allwinner,sun8i-h3-de2-mixer0";quoted
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+ reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0:endpoint at 0quoted
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{quoted
+ reg = <0>; + remote-endpoint =<&tcon0_in_mixer0>;quoted
+ }; + + mixer0_out_tcon1:endpoint at 1quoted
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{quoted
+ reg = <1>; + remote-endpoint =<&tcon1_in_mixer0>;quoted
+ }; + }; + }; + }; + + mixer1: mixer at 1200000 { + compatible ="allwinner,sun8i-h3-de2-mixer1";quoted
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+ reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer1_out_tcon1:endpoint at 0quoted
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{quoted
+ reg = <0>;I would prefer if you could stick to the numbering scheme we're using for Display Engine 1.0, as in endpoint 0 links to component 0 of whatever type.If we keep this we will need a ugly id property in mixer node, otherwise we cannot know which TCON to be bind.Why? You can simply change the logic in your driver from: if (remote_endpoint.id) { continue; } to: if (local_endpoint.id != remote_endpoint.id) { continue; }
Thanks, I forgot that there's two endpoint ids... So silly I am.
I don't see the need for any ID property in the mixer node in this case. The ID is already encoded into the endpoint IDs. ChenYuquoted
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We're probably going to stick to that for the R40's incredibly complicated pipeline. I don't want to have any outliers unless absolutely necessary. ChenYuquoted
+ remote-endpoint =<&tcon1_in_mixer1>;quoted
+ }; + + mixer1_out_tcon0:endpoint at 1quoted
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{quoted
+ reg = <1>; + remote-endpoint =<&tcon0_in_mixer1>;quoted
+ }; + }; + }; + }; + + tcon0: lcd-controller at 1c0c000 { + compatible = "allwinner,sun8i-h3-tcon0"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86IRQ_TYPE_LEVEL_HIGH>;quoted
+ clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch1"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint at 0{quoted
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+ reg = <0>; + remote-endpoint =<&mixer0_out_tcon0>;quoted
+ }; + + tcon0_in_mixer1: endpoint at 1{quoted
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+ reg = <1>; + remote-endpoint =<&mixer1_out_tcon0>;quoted
+ }; + }; + }; + }; + + tcon1: lcd-controller at 1c0d000 { + compatible = "allwinner,sun8i-h3-tcon1"; + reg = <0x01c0d000 0x1000>; + interrupts = <GIC_SPI 87IRQ_TYPE_LEVEL_HIGH>;quoted
+ clocks = <&ccu CLK_BUS_TCON1>; + clock-names = "ahb"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_mixer1: endpoint at 0{quoted
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+ reg = <0>; + remote-endpoint =<&mixer1_out_tcon1>;quoted
+ }; + + tcon1_in_mixer0: endpoint at 1{quoted
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+ reg = <1>; + remote-endpoint =<&mixer0_out_tcon1>;quoted
+ }; + }; + + tcon1_out: port at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_tve0: endpoint at 1{quoted
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+ reg = <1>; + remote-endpoint =<&tve0_in_tcon1>;quoted
+ }; + }; + }; + }; + + tve0: tv-encoder at 1e00000 { + compatible ="allwinner,sun8i-h3-tv-encoder";quoted
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+ reg = <0x01e00000 0x1000>; + clocks = <&ccu CLK_BUS_TVE>, <&ccuCLK_TVE>;quoted
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+ clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_TVE>; + status = "disabled"; + + assigned-clocks = <&ccu CLK_TVE>; + assigned-clock-parents = <&ccu CLK_PLL_DE>; + assigned-clock-rates = <216000000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon1: endpoint at 0 { + reg = <0>; + remote-endpoint =<&tcon1_out_tve0>;quoted
+ }; + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |IRQ_TYPE_LEVEL_LOW)>,quoted
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