On Fri, May 19, 2017 at 7:07 AM, Stephen Boyd [off-list ref] wrote:

On 05/06, Anup Patel wrote:

quoted

From: Sandeep Tripathy <redacted>

This patch adds support for Stingray clocks in iproc
ccf. The Stingray SOC has various plls based on iproc
pll architecture.

Does it have anything besides PLLs?

It describes various plls and soc specific details for the particular
SOC based on
bcm iproc architecture. the core functionality is implemented for all
Broadcom SOC
using iproc pll architecture in generic iproc drivers  eg: clk-iproc-pll.c

quoted

+CLK_OF_DECLARE(sr_genpll0_clk, "brcm,sr-genpll0",
+                             sr_genpll0_clk_init);
+
+static const struct iproc_pll_ctrl genpll3 = {
+     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+             IPROC_CLK_PLL_NEEDS_SW_CFG,
+     .aon = AON_VAL(0x0, 1, 19, 18),
+     .reset = RESET_VAL(0x0, 12, 11),
+     .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+     .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+     .ndiv_int = REG_VAL(0x10, 20, 10),
+     .ndiv_frac = REG_VAL(0x10, 0, 20),
+     .pdiv = REG_VAL(0x14, 0, 4),
+     .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll3_clk[] = {
+     [BCM_SR_GENPLL3_HSLS_CLK] = {
+             .channel = BCM_SR_GENPLL3_HSLS_CLK,
+             .flags = IPROC_CLK_AON,
+             .enable = ENABLE_VAL(0x4, 6, 0, 12),
+             .mdiv = REG_VAL(0x18, 0, 9),
+     },
+     [BCM_SR_GENPLL3_SDIO_CLK] = {
+             .channel = BCM_SR_GENPLL3_SDIO_CLK,
+             .flags = IPROC_CLK_AON,
+             .enable = ENABLE_VAL(0x4, 7, 1, 13),
+             .mdiv = REG_VAL(0x18, 10, 9),
+     },
+};
+
+static void __init sr_genpll3_clk_init(struct device_node *node)
+{
+     iproc_pll_clk_setup(node, &genpll3, NULL, 0, genpll3_clk,
+                             ARRAY_SIZE(genpll3_clk));
+}
+CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3",
+                     sr_genpll3_clk_init);

Can you make this a platform driver instead? Are all these clks
really used for getting the interrupt and timers running?

Not all clocks needed early except the genpll3. sp804 timer clks are derived
from genpll. we will send revised patch to have most of the clocks registered
via platform driver probe.

quoted

+
+static const struct iproc_pll_ctrl genpll4 = {
+     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+             IPROC_CLK_PLL_NEEDS_SW_CFG,
+     .aon = AON_VAL(0x0, 1, 25, 24),
+     .reset = RESET_VAL(0x0, 12, 11),
+     .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+     .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+     .ndiv_int = REG_VAL(0x10, 20, 10),
+     .ndiv_frac = REG_VAL(0x10, 0, 20),
+     .pdiv = REG_VAL(0x14, 0, 4),
+     .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll4_clk[] = {
+     [BCM_SR_GENPLL4_CCN_CLK] = {
+             .channel = BCM_SR_GENPLL4_CCN_CLK,
+             .flags = IPROC_CLK_AON,
+             .enable = ENABLE_VAL(0x4, 6, 0, 12),
+             .mdiv = REG_VAL(0x18, 0, 9),
+     },
+};
+

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regards
Sandeep