[PATCH v3 08/21] clk: sunxi-ng: sun5i: Export video PLLs
STALE3420d
REVIEWED: 1 (0M)
From: Maxime Ripard <hidden>
Date: 2017-05-17 07:45:35
Also in:
dri-devel, linux-clk, linux-devicetree, lkml
Subsystem:
arm/allwinner sunxi soc support, common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Revision v3 of 4 in this series; 1 review trailer.
Revisions (4)
- v1 [diff vs current]
- v2 [diff vs current]
- v3 current
- v4 [diff vs current]
The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Maxime Ripard <redacted> Acked-by: Chen-Yu Tsai <redacted> --- drivers/clk/sunxi-ng/ccu-sun5i.h | 6 ++++-- include/dt-bindings/clock/sun5i-ccu.h | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h
index 8144487eb7ca..93a275fbd9a9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.h
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.h@@ -28,15 +28,17 @@ #define CLK_PLL_AUDIO_4X 6 #define CLK_PLL_AUDIO_8X 7 #define CLK_PLL_VIDEO0 8 -#define CLK_PLL_VIDEO0_2X 9 + +/* The PLL_VIDEO0_2X is exported for HDMI */ + #define CLK_PLL_VE 10 #define CLK_PLL_DDR_BASE 11 #define CLK_PLL_DDR 12 #define CLK_PLL_DDR_OTHER 13 #define CLK_PLL_PERIPH 14 #define CLK_PLL_VIDEO1 15 -#define CLK_PLL_VIDEO1_2X 16 +/* The PLL_VIDEO1_2X is exported for HDMI */ /* The CPU clock is exported */ #define CLK_AXI 18
diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
index aeb2e2f781fb..81f34d477aeb 100644
--- a/include/dt-bindings/clock/sun5i-ccu.h
+++ b/include/dt-bindings/clock/sun5i-ccu.h@@ -19,6 +19,9 @@ #define CLK_HOSC 1 +#define CLK_PLL_VIDEO0_2X 9 + +#define CLK_PLL_VIDEO1_2X 16 #define CLK_CPU 17 #define CLK_AHB_OTG 23
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