On Fri, Mar 31, 2017 at 8:52 AM, zhichang.yuan
[off-list ref] wrote:

Hi, Rafael,

Thanks for reviewing this!

On 2017/3/31 4:31, Rafael J. Wysocki wrote:

quoted

On Thursday, March 30, 2017 11:26:58 PM zhichang.yuan wrote:

quoted

On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O
with some special host-local I/O ports known on x86. To access the I/O
peripherals, an indirect-IO mechanism is introduced to mapped the host-local
I/O to system logical/fake PIO similar the PCI MMIO on architectures where no
separate I/O space exists. Just as PCI MMIO, the host I/O range should be
registered before probing the downstream devices and set up the I/O mapping.
But current ACPI bus probing doesn't support these indirect-IO hosts/devices.

This patch introdueces a new ACPI handler for this device category. Through the
handler attach callback, the indirect-IO hosts I/O registration is done and
all peripherals' I/O resources are translated into logic/fake PIO before
starting the enumeration.

Can you explain to me briefly what exactly this code is expected to be doing?

As you know currently for ARM architecture IO space is memory mapped and
is only used by pci devices. The port number is dynamically allocated
converting the device IO address into a PIO token: i.e.
http://lxr.free-electrons.com/source/drivers/acpi/pci_root.c#L745
This patch is meant to support a new class of IO host controller
that are not PCI based and that still require to have the IO addresses
be translated in the same PIO token space as the PCI controller

IOW, this is ARM-specific, right?

Thanks,
Rafael