[PATCH] irqchip/gic-v3: Fix GICD_CTLR_ARE_NS bit field
From: alim.akhtar@samsung.com (Alim Akhtar)
Date: 2017-03-07 04:42:49
Also in:
lkml, stable
Subsystem:
arm generic interrupt controller drivers, the rest · Maintainers:
Marc Zyngier, Linus Torvalds
Possibly related (same subject, not in this thread)
- 2017-03-07 · Re: [PATCH] irqchip/gic-v3: Fix GICD_CTLR_ARE_NS bit field · Alim Akhtar <alim.akhtar@samsung.com>
- 2017-03-07 · Re: [PATCH] irqchip/gic-v3: Fix GICD_CTLR_ARE_NS bit field · Marc Zyngier <hidden>
From: Alim Akhtar <redacted>
As per GICv3 Architecture specification 8.9.4 field descriptions,
GICD_CTLR_ARE_NS is bit[5]. This patch correct the same.
Fixes: 021f6537 ("irqchip: gic-v3: Initial support for GICv3")
Cc: stable at vger.kernel.org
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
include/linux/irqchip/arm-gic-v3.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index e808f8a..4aaf639 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h@@ -57,7 +57,7 @@ #define GICD_CTLR_RWP (1U << 31) #define GICD_CTLR_DS (1U << 6) -#define GICD_CTLR_ARE_NS (1U << 4) +#define GICD_CTLR_ARE_NS (1U << 5) #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0)
--
2.7.4