Hi,
On Wed, 2017-02-22 at 12:36 +0300, Sergei Shtylyov wrote:

On 2/22/2017 11:55 AM, Chunfeng Yun wrote:

quoted

there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is 26M which usually comes from 26M oscillator
directly, but some SoCs is not. it is flexible to move it into port

    ... but on some SoCs does not?

I mean the reference clock of SuperSpeed port comes from PLL and need be
controlled by driver on some SoCs. When it comes from oscillator
directly, it is optional and is ok whether the driver controll it or not

quoted

node.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

[...]

MBR, Sergei