Hi Gregory,

Gregory CLEMENT [off-list ref] writes:

From: Romain Perier <redacted>

Some Marvell ethernet switches have internal ethernet transceivers with
hardcoded phy addresses. These addresses can be greater than the number
of ports or its value might be different than the associated port number.
This is for example the case for MV88E6341 that has 6 ports and internal
Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14.

Isn't there an hardware table used to map the PHY addresses on such chip?

This commits fixes the issue by removing the condition in MDIO callbacks.

Signed-off-by: Romain Perier <redacted>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <redacted>

The patch is anyway still valid:

Reviewed-by: Vivien Didelot <redacted>

Thanks,

        Vivien