[PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
From: Lee Jones <hidden>
Date: 2017-01-03 17:46:28
Also in:
linux-devicetree, lkml
On Tue, 06 Dec 2016, Andrew Jeffery wrote:
The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux drivers. Signed-off-by: Andrew Jeffery <redacted>
Applied with Acks, thanks.
quoted hunk ↗ jump to hunk
--- .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index a97131aba446..9de318ef72da 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt@@ -109,3 +109,25 @@ lpc: lpc at 1e789000 { }; }; +Host Node Children +================== + +LPC Host Controller +------------------- + +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour +between the host and the baseboard management controller. The registers exist +in the "host" portion of the Aspeed LPC controller, which must be the parent of +the LPC host controller node. + +Required properties: +- compatible: "aspeed,ast2500-lhc"; +- reg: contains offset/length value of the LHC memory + region. + +Example: + +lhc: lhc at 20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; +};
-- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog