On Mon, Jan 02, 2017 at 09:36:10AM +0000, Rafal Ozieblo wrote:
According Cadence Hardware team:
"It is just that some customers prefer to have the time in the descriptors as that is provided per frame.
The registers are simply overwritten when a new event frame is transmitted/received and so software could miss it."
The question is are you sure that you read timestamp for current frame? (not for the next frame).
AFAICT, having the time stamp in the descriptor is not universally
supported. Looking at the Xilinx Zynq 7000 TRM, I can't find any
mention of this.
This Cadence IP core is a complete disaster.
Unless someone can tell us how this IP works in all of its
incarnations, this series is going nowhere.
Thanks,
Richard