[PATCH 1/2] clk: samsung: exynos4412: add cpu clock configuration data for Exynos4412 Prime
From: Bartlomiej Zolnierkiewicz <hidden>
Date: 2016-12-29 13:37:36
Also in:
linux-clk, linux-pm, linux-samsung-soc, lkml
Subsystem:
common clk framework, samsung soc clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Linus Torvalds
Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Cc: Doug Anderson <dianders@chromium.org> Cc: Andreas Faerber <afaerber@suse.de> Cc: Thomas Abraham <redacted> Cc: Tobias Jakobi <redacted> Cc: Ben Gamari <redacted> Signed-off-by: Bartlomiej Zolnierkiewicz <redacted> --- drivers/clk/samsung/clk-exynos4.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index faab9b3..e40b775 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c@@ -1298,6 +1298,8 @@ static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) }; static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { + PLL_35XX_RATE(1704000000, 213, 3, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), PLL_35XX_RATE(1500000000, 250, 4, 0), PLL_35XX_RATE(1400000000, 175, 3, 0), PLL_35XX_RATE(1300000000, 325, 6, 0),
@@ -1421,6 +1423,8 @@ static void __init exynos4x12_core_down_clock(void) (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { + { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), }, + { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
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1.9.1