Sebastian Frias [off-list ref] writes:
On 24/11/16 19:55, Florian Fainelli wrote:
quoted
Le 24/11/2016 ? 09:05, Martin Blumenstingl a ?crit :
quoted
Based on what I found it seems that rgmii-id, rgmii-txid and
rgmii-rxid are supposed to be handled by the PHY.
Correct, the meaning of PHY_INTERFACE_MODE should be from the
perspective of the PHY device:
- PHY_INTERFACE_MODE_RGMII_TXID means that the PHY is responsible for
adding a delay when the MAC transmits (TX MAC -> PHY (delay) -> wire)
- PHY_INTERFACE_MODE_RGMII_RXID means that the PHY is responsible for
adding a delay when the MAC receives (RX MAC <- (delay) PHY) <- wire)
Thanks for the explanation.
Actually I had thought that the delay was to account for board routing
(wires) between the MAC and the PHY.
From your explanation it appears that the delay is to account for board
routing (wires) between the PHY and the RJ45 socket.
The delay pertains to the RGMII link between MAC and PHY. The external
connection is self-clocking.
--
M?ns Rullg?rd