[PATCH] gpio: Added zynq specific check for special pins on bank zero

On 20.9.2016 16:06, S?ren Brinkmann wrote:

On Tue, 2016-09-20 at 14:02:04 +0530, Nava kishore Manne wrote:

quoted

From: Nava kishore Manne <redacted>

This patch adds zynq specific check for bank 0 pins 7 and 8
are special and cannot be used as inputs

Signed-off-by: Nava kishore Manne <redacted>
---
 drivers/gpio/gpio-zynq.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
index e72794e..eae9d24 100644
--- a/drivers/gpio/gpio-zynq.c
+++ b/drivers/gpio/gpio-zynq.c

@@ -96,6 +96,10 @@
 /* GPIO upper 16 bit mask */
 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
 
+/* For GPIO quirks */
+#define ZYNQ_GPIO	BIT(0)
+#define ZYNQMP_GPIO	BIT(1)

I'd make sure all quirks are easily identifiable and call them something
like 'ZYNQ_GPIO_QUIRK_FOO'

Apart from that:
Acked-by: S?ren Brinkmann <redacted>

This issue was:
Reported-by: Jonas Karlsson <redacted>

And here is also my:
Acked-by: Michal Simek <redacted>

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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