[PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

On 26/08/16 18:00, Catalin Marinas wrote:

On Fri, Aug 26, 2016 at 05:16:27PM +0100, Will Deacon wrote:

quoted

On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote:

quoted

On 26/08/16 14:04, Suzuki K Poulose wrote:

quoted

It might be worth looking to see if we can pass the ctr as an extra
parameter to the assembly routines that need it. Then you can access it
easily from C code, and if you pass it as 0 that could result in the asm
code reading it from the h/w register, removing the need for the _raw
stuff you add.

How often to we need to access a sanitised sysreg from assembly? AFAICT,
CTR_EL0 is the first. If we only need it to infer the minimum cache line
size, we could as well store the latter in a global variable and access
it directly. If we feel brave, we could patch a "mov \reg, #x"
instruction in the ?cache_line_size macros (starting with 32 by default,
though to make it less cumbersome we'd have to improve the run-time
patching code a bit).

With Ard's patches [1] to refactor the feature array, we can refer to named
CTR_EL0 feature register cleanly. I can rebase this series on top of that
if nobody has any objection.

[1] http://marc.info/?l=linux-arm-kernel&m=147263959504998&w=2


Suzuki