[v7 PATCH 4/6] arm64: dts: rockchip: add Type-C phy for RK3399
From: Guenter Roeck <hidden>
Date: 2016-07-27 21:50:35
Also in:
linux-devicetree, linux-rockchip, lkml
On Wed, Jul 27, 2016 at 6:07 AM, Chris Zhong [off-list ref] wrote:
There are 2 Type-C phy on RK3399, they are almost same, except the address of register. They support USB3.0 Type-C and DisplayPort1.3 Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller and DP controller. Signed-off-by: Chris Zhong <redacted>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
quoted hunk ↗ jump to hunk
--- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Changes in v1: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 44 ++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 0af03a3..7095ddf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi@@ -952,6 +952,50 @@ }; }; + tcphy0: phy at ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + rockchip,grf = <&grf>; + #phy-cells = <0>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,typec-conn-dir = <0xe580 0 16>; + rockchip,usb3tousb2-en = <0xe580 3 19>; + rockchip,external-psm = <0xe588 14 30>; + rockchip,pipe-status = <0xe5c0 0 0>; + rockchip,uphy-dp-sel = <0x6268 19 19>; + status = "disabled"; + }; + + tcphy1: phy at ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + rockchip,grf = <&grf>; + #phy-cells = <0>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,typec-conn-dir = <0xe58c 0 16>; + rockchip,usb3tousb2-en = <0xe58c 3 19>; + rockchip,external-psm = <0xe594 14 30>; + rockchip,pipe-status = <0xe5c0 16 16>; + rockchip,uphy-dp-sel = <0x6268 3 19>; + status = "disabled"; + }; + watchdog at ff840000 { compatible = "snps,dw-wdt"; reg = <0x0 0xff840000 0x0 0x100>; --2.6.3