Hi Will,

On 25 July 2016 at 17:02, Will Deacon [off-list ref] wrote:

On Wed, Jul 20, 2016 at 02:17:59AM +0800, fu.wei at linaro.org wrote:

quoted

From: Fu Wei <redacted>

This patch simplify arch_counter_get_cntvct_mem function by
using readq to get 64-bit CNTVCT value instead of readl_relaxed.

Signed-off-by: Fu Wei <redacted>
---
 drivers/clocksource/arm_arch_timer.c | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index e6fd42d..483d2f9 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c

@@ -418,15 +418,7 @@ u32 arch_timer_get_rate(void)

 static u64 arch_counter_get_cntvct_mem(void)
 {
-     u32 vct_lo, vct_hi, tmp_hi;
-
-     do {
-             vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
-             vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
-             tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
-     } while (vct_hi != tmp_hi);
-
-     return ((u64) vct_hi << 32) | vct_lo;
+     return readq(arch_counter_base + CNTVCT_LO);

Sorry, right after posting v9, I got your comment,

What's the benefit of doing this? If you use readq here, how can we

benefit:
1. simplify the code
2. from arch/arm64/include/asm/io.h, I guess readq is more efficient

guarantee that (a) the endpoint won't generate a SLVERR or similar and
(b) that we get ?

I think so, according to arch/arm64/include/asm/io.h.
readq Implement by "LDR" and "LDAR", So I think It is an atomic read.

Please correct me, If I misunderstand something, thanks

"If it ain't broke, don't fix it"

Will

-- 
Best regards,

Fu Wei
Software Engineer
Red Hat