[PATCH 8/8] arm64:perf: L3 cache(LLC) event listing in perf

	1. Add L3 caches events to /sys/devices/hisi_l3c/events/
	   The events can be selected as shown in perf list
	   e.g.: For LLC_READ_ALLOCATE event for Super CPU cluster 2 the
		 event format is
		 -e "hisi_l3c/l3c_read_allocate,bank=0xf,cluster=0x2/"

Signed-off-by: Anurup M <redacted>
Signed-off-by: Shaokun Zhang <redacted>
---
 drivers/perf/hisilicon/hisi_uncore_llc.c | 75 +++++++++++++++++++++++++++++++-
 drivers/perf/hisilicon/hisi_uncore_pmu.c | 12 +++++
 drivers/perf/hisilicon/hisi_uncore_pmu.h | 16 +++++++
 3 files changed, 101 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/hisilicon/hisi_uncore_llc.c b/drivers/perf/hisilicon/hisi_uncore_llc.c
index a771e1a..316167a 100644
--- a/drivers/perf/hisilicon/hisi_uncore_llc.c
+++ b/drivers/perf/hisilicon/hisi_uncore_llc.c

@@ -25,11 +25,11 @@
 #include "hisi_uncore_llc.h"
 
 /* Map cfg_en values for LLC Banks */
-const int llc_cfgen_map[] = { HISI_LLC_BANK0_CFGEN, HISI_LLC_BANK1_CFGEN,
+static const int llc_cfgen_map[] = { HISI_LLC_BANK0_CFGEN, HISI_LLC_BANK1_CFGEN,
 				HISI_LLC_BANK2_CFGEN, HISI_LLC_BANK3_CFGEN
 };
 
-struct hisi_pmu *hisi_uncore_llc;
+static struct hisi_pmu *hisi_uncore_llc;
 
 static inline int hisi_llc_counter_valid(int idx)
 {

@@ -442,6 +442,76 @@ static void hisi_free_llc_data(struct hisi_hwmod_unit *punit)
 	kfree(punit->hwmod_data);
 }
 
+PMU_FORMAT_ATTR(event, "config:0-11");
+PMU_FORMAT_ATTR(bank, "config:12-15");
+PMU_FORMAT_ATTR(module, "config:16-19");
+PMU_FORMAT_ATTR(cluster, "config:20-23");
+PMU_FORMAT_ATTR(socket, "config:24-25");
+
+#define HISI_UNCORE_EVENT_DESC(_name, _config)			\
+{								\
+	.attr   = __ATTR(_name, 0444, uncore_event_show, NULL), \
+	.config = _config,					\
+}
+
+static struct attribute *hisi_llc_format_attr[] = {
+	&format_attr_event.attr,
+	&format_attr_bank.attr,
+	&format_attr_module.attr,
+	&format_attr_cluster.attr,
+	&format_attr_socket.attr,
+	NULL,
+};