On 06/01, Geert Uytterhoeven wrote:

	Hi all,

Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
state of the mode pins either by a call from the board code, or directly
by using a hardcoded register access. This is a bit messy, and creates a
dependency between driver and platform code.

This RFC patch series converts the various Renesas R-Car clock drivers
and support code from reading the mode pin states using a hardcoded
register access to using a new R-Car RST driver.

Dumb question, can we use the nvmem reading APIs instead of an
SoC specific function to read the modes?

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