On 06/02, charanya at codeaurora.org wrote:

On 2016-05-26 04:16, Stephen Boyd wrote:

quoted

Ok, but what's the exact sequence of events that happens? I think
we unlock the spinlock in the dma completion handler and then the
txlev interrupt runs? At that point we may have more data to push
out and then rx stale handling runs and corrupts the fifo state?

I was hoping for some sort of CPU sequence of events like:

CPU0                   CPU1
----                   ----

msm_start_rx_dma()
                      msm_complete_rx_dma()
	        spin_unlock_irqrestore(&port->lock)
msm_uart_irq()
 msm_handle_rx_dm()
  <Read from FIFO and breaks>

This patch seems correct, but the commit text isn't fully
describing the sequence of events that causes this to happen, so
it's taking a while to convince myself that this patch fixes
anything.

The sequence of events is as mentioned. When the TXLEV interrupt
occurs after the
spinlock is unlocked, the rx stale handling runs since the
interrupts are restored
and hence it corrupts the fifo state.

Ok, care to put such information into the commit text of the
patch and resend then please? It will help us later to recall
what the actual problem was.

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