[PATCH 08/23] ARM: dts: r8a7794: Fix W=1 dtc warnings
From: geert+renesas@glider.be (Geert Uytterhoeven)
Date: 2016-05-13 07:55:48
Also in:
linux-devicetree, linux-renesas-soc
Subsystem:
the rest · Maintainer:
Linus Torvalds
Warning (unit_address_vs_reg): Node /cache-controller at 1 has a unit name, but no reg property Move the cache-controller node under the cpus node, and make its unit name and reg property match the MPIDR value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- arch/arm/boot/dts/r8a7794.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index f334a3a715f27d12..cff1c5aa0ec48950 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi@@ -55,13 +55,14 @@ power-domains = <&sysc R8A7794_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; - }; - L2_CA7: cache-controller at 1 { - compatible = "cache"; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; + L2_CA7: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7794_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; }; gic: interrupt-controller at f1001000 {
--
1.9.1