[PATCH 4/6] pwm: pwm-lpc18xx-sct: test clock rate to avoid division by 0
From: Joachim Eastwood <hidden>
Date: 2016-03-02 22:44:06
Also in:
linux-pwm, linux-renesas-soc, lkml
Hi Wolfram, On 2 March 2016 at 23:33, Wolfram Sang [off-list ref] wrote:
quoted hunk ↗ jump to hunk
From: Wolfram Sang <wsa+renesas@sang-engineering.com> The clk API may return 0 on clk_get_rate, so we should check the result before using it as a divisor. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Should go individually via subsystem tree. drivers/pwm/pwm-lpc18xx-sct.c | 2 ++ 1 file changed, 2 insertions(+)diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c index 9163085101bc94..6487962c355c03 100644 --- a/drivers/pwm/pwm-lpc18xx-sct.c +++ b/drivers/pwm/pwm-lpc18xx-sct.c@@ -360,6 +360,8 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev) } lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk); + if (!lpc18xx_pwm->clk_rate) + return -EINVAL;
This needs to be:
if (!lpc18xx_pwm->clk_rate) {
ret = -EINVAL;
goto disable_pwmclk;
}
I would also prefer an explicit check against 0 here. ie.:
'lpc18xx_pwm->clk_rate == 0'
A dev_err() message would also be nice to have.
regards,
Joachim Eastwood