[PATCH] irqchip/gic-v3-its: Fix double EOIR write for LPI in EOImode==1

On 11/02/16 13:38, Ashok Kumar wrote:

CPU receives SError exception EOI1_NO_INTS_ACTIVE when EOIR
is written twice in gic_handle_irq and in its_eoi_irq for a
single LPI in EOImode == 1.

Now irq_eoi of its_irq_chip calls parent irqchip's(gic_eoimode1_chip/gic_chip)
irq_eoi handler which handles EOImode 0 and 1 separately.

This is introduced by
commit 0b996fd35957a ("irqchip/GICv3: Convert to EOImode == 1")

Signed-off-by: Ashok Kumar <redacted>

Ah, really good catch!

Acked-by: Marc Zyngier <redacted>

I'll try to queue that for -rc4, but it is more likely that it will land
in -rc5...

Thanks,

	M.
-- 
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