On Mon, 1 Feb 2016 21:17:54 +0100
Maxime Ripard [off-list ref] wrote:

quoted

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
'pll8x2' clock with 'pll8' as a divider?

No one seems to use it. We can always add it later in a separate
patch when someone will.

Well, then, I don't understand. The pll periph/peripheral/periph0,
aka PLL6 works well for many SoCs and there is no need to change
its DT definition.

In the patch header, you wrote:

Remove the fixed dividers from the PLL6 driver to be able to have a
reusable driver that can be used across several SoCs that share the same
controller, but don't have the same set of dividers for this clock, and to
also be reused multiple times in the same SoC, since we're droping the
clock name.

then, for the H3, you do
(the comment should be "until pll8 can be reused"),

-		/* dummy clock until pll6 can be reused */
-		pll8: pll8_clk {
+		pll8: clk at 01c20044 {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c20044 0x4>;
+			clocks = <&osc24M>;
 			clock-output-names = "pll8";
 		};

that is, you add the PLL8, don't you?

And, further, you change the MMC clocks:

where the PLL8 is already used.

So, how can you say

No one seems to use it. We can always add it later in a separate
patch when someone will.

?

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