On Sat, Feb 6, 2016 at 5:37 PM, Jean-Francois Moine [off-list ref] wrote:

On Fri, 5 Feb 2016 10:39:15 +0100
Maxime Ripard [off-list ref] wrote:

quoted

quoted

+CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-display-clk", sun6i_display_setup);

Please use the display driver from my DRM serie, it covers everything
you need here.

If you give me a pointer, I will have a look.

quoted

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+CLK_OF_DECLARE(sun6i_pll3, "allwinner,sun6i-pll3-clk", sun6i_pll3_setup);

And please use the clk-factors code here.

I don't see how I can get direct 297MHz and 270MHz in fractional mode
with that code.

clk-factors now supports a custom .recalc callback. Along with get_factors,
you can support pretty much any clock that has four variables, not including
the mux and clock gate.

So for this you'd have the div as factor m, and the integer mode bit as p,
and the fraction bit as n, and recalc would be somewhat like this:

if (p) {
        rate = parent_rate / (m + 1);
} else if (n) {
        rate = 297000000;
} else {
        rate = 270000000;
}

get_factors should be easy enough to figure out.

Regards
ChenYu