[PATCH v4 4/5] arm64/perf: Enable PMCR long cycle counter bit
From: Jan Glauber <hidden>
Date: 2016-02-22 12:45:31
Also in:
lkml
From: Jan Glauber <hidden>
Date: 2016-02-22 12:45:31
Also in:
lkml
On Thu, Feb 18, 2016 at 05:34:28PM +0000, Will Deacon wrote:
On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glauber wrote:quoted
With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated. To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before. Original patch from Andrew Pinksi [off-list ref]What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?
Hi Will, Please let me know if I should repost or not, FWIW I got Andrew's S-o-B on the patch. Thanks, Jan
Will