Ok, I'll send the incremental patch out again.

Thanks,
Suravee

On 2/12/16 04:23, Olof Johansson wrote:

Hi,

On Wed, Feb 10, 2016 at 1:13 PM, Suravee Suthikulpanit
[off-list ref] wrote:

quoted

Hi Arnd,


On 2/9/16 21:57, Arnd Bergmann wrote:

quoted

On Monday 08 February 2016 11:59:08 Suravee Suthikulpanit wrote:

quoted

From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Fix DMA ranges of smb0 and pcie0 nodes in AMD Seattle SOC.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

This could use a changelog text to explain why it's broken and how the
fix works.

         Arnd

So, I have not experience the breakage. However, IIUC, the GICv2m MSI frame
is also considered DMA-able. So, I think it should be included in the
dma-range specified here. Please let me know if my assumption is incorrect.
Otherwise, I will include more description in the commit log in my next rev.

As I replied when I did it -- I've applied the patches, so respinning
won't work. Instead, please follow up with incremental fixes to this
series instead.


Thanks,

-Olof