On Thursday, January 07, 2016 at 09:56:06 AM, Ley Foon Tan wrote:

On Tue, 2016-01-05 at 14:49 +0100, Marek Vasut wrote:

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On Tuesday, January 05, 2016 at 02:18:18 AM, Ley Foon Tan wrote:

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On Tue, 2016-01-05 at 01:47 +0100, Marek Vasut wrote:

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On Tuesday, January 05, 2016 at 01:45:45 AM, Ley Foon Tan wrote:

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On Mon, 2016-01-04 at 02:12 +0100, Marek Vasut wrote:

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On Monday, January 04, 2016 at 01:53:22 AM, Ley Foon Tan wrote:

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On Mon, 2016-01-04 at 01:37 +0100, Marek Vasut wrote:

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On Monday, January 04, 2016 at 01:10:13 AM, Ley Foon Tan
wrote:

Hi!

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Well, do you have a good explanation why the system
works with this change and doesn't work without it
on my design ? I'd really love to understand this.

Do you modify the driver to setup the translation
table?

No, I didn't change the driver. What do you refer to
please ?

There is Address Translation Table at address offset 0x1000
in the IP.

Oh, I didn't configure that in any way. Should I or does the
driver configure it in some way?

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Do you use the hardware design from the rocketboards.org or
your own design?

I use the one from rocketboards, I just ported it over to the
MCVEVK (custom cyclone v soc board)

You may check again the base addresses use in the MCVEVK board.

The address map is attached ; I don't see anything which would
differ from the reference design.

Address map looks fine.

Well do you have any other idea then ? I guess I should pull out the
SOCDK, huh?

Can't think of any other thing that impact this, I expect the bus width
used in the pipeline/bridge are same with the example design.
Do you have our CV, AV or A10 SoC devkit?

I tested CV SoCDK just now and you're right, the provided quartus project
works without this change on the CV SoCDK. Do you have any suggestion for
me where I should try looking then please ?

Do you check the hardware pipeline bridge in Qsys? Are they same
configuration as CV SoCDK design?

If you mean ccb_h2f_50_to_125 , then yes, they are exactly the same.

The only difference I can think of is in altr_xcvr_reconfig_0 , where I have
2 reconfiguration interfaces instead of 5 because I am using only PCIe x1
instead of x4 as it is on the CV SoCDK. The pcie_cv_hip_avmm_0 is configured
exactly the same too (but for x1 Gen1 port instead of x4 Gen1 port).

Best regards,
Marek Vasut