Hi Tero,

On 12/16, Tony Lindgren wrote:

* Tero Kristo [off-list ref] [151216 01:00]:

quoted

Errata i810 states that DPLL controller can get stuck while transitioning
to a power saving state, while its M/N ratio is being re-programmed.

As a workaround, before re-programming the M/N ratio, SW has to ensure
the DPLL cannot start an idle state transition. SW can disable DPLL
idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
active by setting a dependent clock domain in SW_WKUP.

This errata is known to impact OMAP5 and DRA7 chips, but lets enable it
unconditionally to avoid any potential problems with earlier generation
SoCs also.

Signed-off-by: Tero Kristo <redacted>
---
v2: made the fix to be applied unconditionally on all OMAP3+ SoCs

Thanks looks good to me now:

Acked-by: Tony Lindgren <tony@atomide.com>

Patch looks good to me too.

Stephen and I were discussing clk pull requests, more specifically how
to vet the contents of them. So we came up with the idea to add our acks
to patches that we take into our tree, but that we expect to get batched
up into a pull request. To that end:

Acked-by: Michael Turquette <mturquette@baylibre.com>

Regards,
Mike