"Suzuki K. Poulose" [off-list ref] writes:
Add ARM CoreLink CCI-550 cache coherent interconnect PMU
driver support. The CCI-550 PMU shares all the attributes of CCI-500
PMU, except for an additional master interface (MI-6 - 0xe).
CCI-550 requires the same work around as for CCI-500 to
write to the PMU counter.
Cc: Punit Agrawal <redacted>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
---
Documentation/devicetree/bindings/arm/cci.txt | 2 +
drivers/bus/Kconfig | 8 +--
drivers/bus/arm-cci.c | 85 ++++++++++++++++++++++++-
3 files changed, 90 insertions(+), 5 deletions(-)
Acked-by: Punit Agrawal <redacted>
Thanks,
Punit