[PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
From: Bartlomiej Zolnierkiewicz <hidden>
Date: 2015-12-15 17:36:40
Also in:
linux-pm, linux-samsung-soc, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Thomas Abraham <redacted> For Exynos542x/5800 platforms, add CPU operating points for migrating from Exynos specific cpufreq driver to using generic cpufreq driver. Changes by Bartlomiej: - split Exynos5420 support from the original patch - merged Exynos5422 fixes from Ben Changes by Ben Gamari: - Port to operating-points-v2 Cc: Kukjin Kim <redacted> Cc: Doug Anderson <dianders@chromium.org> Cc: Javier Martinez Canillas <redacted> Cc: Andreas Faerber <afaerber@suse.de> Signed-off-by: Thomas Abraham <redacted> Signed-off-by: Ben Gamari <redacted> Signed-off-by: Bartlomiej Zolnierkiewicz <redacted> --- arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 +++ arch/arm/boot/dts/exynos5420.dtsi | 110 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++ 3 files changed, 130 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 7aaf031..261d251 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi@@ -29,8 +29,10 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu1: cpu at 1 {
@@ -39,6 +41,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu2: cpu at 2 {
@@ -47,6 +50,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu3: cpu at 3 {
@@ -55,14 +59,17 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu4: cpu at 100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu5: cpu at 101 {
@@ -71,6 +78,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu6: cpu at 102 {
@@ -79,6 +87,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu7: cpu at 103 {
@@ -87,6 +96,7 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; }; };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 29b7cba..2458bdf 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi@@ -50,6 +50,116 @@ usbdrdphy1 = &usbdrd_phy1; }; + cluster_a15_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp at 1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp at 1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp at 1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1175000>; + clock-latency-ns = <140000>; + }; + opp at 1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <140000>; + }; + opp at 1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp at 1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp at 1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <140000>; + }; + opp at 1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp at 1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = < 987500>; + clock-latency-ns = <140000>; + }; + opp at 900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = < 962500>; + clock-latency-ns = <140000>; + }; + opp at 800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = < 937500>; + clock-latency-ns = <140000>; + }; + opp at 700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = < 912500>; + clock-latency-ns = <140000>; + }; + }; + + cluster_a7_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp at 1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp at 1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp at 1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1162500>; + clock-latency-ns = <140000>; + }; + opp at 1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp at 900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp at 800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp at 700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp at 600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + }; + /* * The 'cpus' node is not present here but instead it is provided * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 33028ac..9b46b9f 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi@@ -28,8 +28,10 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu1: cpu at 101 {
@@ -38,6 +40,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu2: cpu at 102 {
@@ -46,6 +49,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu3: cpu at 103 {
@@ -54,14 +58,17 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cluster_a7_opp_table>; }; cpu4: cpu at 0 { device_type = "cpu"; compatible = "arm,cortex-a15"; + clocks = <&clock CLK_ARM_CLK>; reg = <0x0>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu5: cpu at 1 {
@@ -70,6 +77,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu6: cpu at 2 {
@@ -78,6 +86,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; cpu7: cpu at 3 {
@@ -86,6 +95,7 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cluster_a15_opp_table>; }; }; };
--
1.9.1