On Sun, Nov 29, 2015 at 02:10:01PM +0200, Dmitry Lifshitz wrote:
Hi Nishanth,
Thank you for the provided feedback.
On 11/25/2015 11:36 PM, Nishanth Menon wrote:
quoted
On 11/25/2015 12:39 AM, Dmitry Lifshitz wrote:
[...]
quoted
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
new file mode 100644
index 0000000..b11d7da
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
[...]
quoted
+/ {
+ model = "CompuLab CL-SOM-AM57x";
+ compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
I think if you like to enable LPAE, the format might look a little
different..
We would like to have a basic HW support in the mainline. It might be
enhanced later, once we get to work on LPAE stuff.
I think what is meant here is the cell sizes should be 2 instead of 1.
You can do that independent of LPAE support. I would expect the base SOC
dtsi file to set the cell sizes correctly though.
Rob