[PATCH 2/2] pinctrl: sunxi: Add irq pinmuxing to sun6i "r" pincontroller
From: Hans de Goede <hidden>
Date: 2015-10-15 14:27:26
Also in:
linux-devicetree
Subsystem:
arm/allwinner sunxi soc support, pin control subsystem, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij, Linus Torvalds
Possibly related (same subject, not in this thread)
- 2015-10-16 · Re: [PATCH 2/2] pinctrl: sunxi: Add irq pinmuxing to sun6i "r" pincontroller · Chen-Yu Tsai <hidden>
Add pinmuxing for external interrupt functionality through the sun6i "r" pincontroller. Signed-off-by: Hans de Goede <redacted> --- drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 9596b0a3..88bd20f 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c@@ -47,45 +47,57 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0), /* PM_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1), /* PM_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */ SUNXI_FUNCTION(0x3, "1wire")), SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3), /* PM_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4), /* PM_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5), /* PM_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6), /* PM_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */ SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */ };
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2.5.0