[PATCH v2 4/4] arm64: document the cache policy behavior
From: Will Deacon <hidden>
Date: 2015-10-30 12:08:25
Also in:
stable
On Thu, Oct 29, 2015 at 04:20:42PM -0700, Alex Van Brunt wrote:
Add a comment that clairfies how the kernel should behave given the cache
clarifies
quoted hunk ↗ jump to hunk
policy reported by the CPU. Signed-off-by: Alex Van Brunt <redacted> Cc: <redacted> --- arch/arm64/kernel/cpuinfo.c | 8 ++++++++ 1 file changed, 8 insertions(+)diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index ae04ac1..bf7e5e2 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c@@ -49,6 +49,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) unsigned int cpu = smp_processor_id(); u32 l1ip = CTR_L1IP(info->reg_ctr); + /* + * The ARM architecture defines PIPT, VIPT and AIVIVT in terms of the
-the
+ * the observable behavior not how the CPU implements the policy.
s/not/rather than/
+ * Specifically, the policies differentiate the correct way to + * invalidate the cache. The definitions say that the only + * architecturally guaranteed way to invalidate a VIPT or AIVIVT + * instruction cache is to invalidate the entire instruction cache. + */ if (l1ip != ICACHE_POLICY_PIPT) set_bit(ICACHEF_ALIASING, &__icache_flags); if (l1ip == ICACHE_POLICY_AIVIVT)
With the minor cosmetic changes: Acked-by: Will Deacon [off-list ref] although I don't see how we can really apply this given that we're not planning to revert the cache geometry stuff. Maybe you could spin a separate series just addressing the aliasing I-cache detection, then we can build on top of that? Will