The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske <redacted>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-bus-gates.c                 | 105 ++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c                     |  12 ++-
 4 files changed, 117 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-bus-gates.c

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7c4aee0..6293c65 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c

@@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,

                for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
                                                clk_name[i] != '_' &&
-                                               clk_name[i] != '\0'; i++) {
+                                               clk_name[i] != '\0'; i++)
                        base_name[i] = clk_name[i];
-               }

                base_name[i] = '\0';
                factors.name = base_name;