Russell King - ARM Linux [off-list ref] writes:
quoted
Moreover, this is consistent with the fact that this commit is in linux-next but
not in v4.1 :
a5e090acbf54 ("ARM: software-based priviledged-no-access support")
So the issue is around this SW_DOMAIN_PAN, at least on PXA.
Is it only PXA which seems to be affected?
Sorry I don't know, I only own pxa platforms.
If so, you may need to add:
mrc p15, 0, \rd, c2, c0, 0
mov \rd, \rd
sub pc, pc, #4
to the places we update the domain access register to ensure that the
Xscale pipeline stalls to allow the CP15 DACR update to hit.
Okay, I'll try that.
By the way, the ARMv5 manual states in chapter "B4.5.1 MMU Fault" that for a
DACR update, a "PrefetchFlush" operation has to be done (chapter B2.6.3
PrefetchFlush CP15 register 7), quoting :
Changes to the Domain Access Control register are synchronized by performing
a PrefetchFlush operation (or as result of an exception or exception
return). See Changes to CP15 registers and the memory order model on page
B2-24 for details.
Cheers.
--
Robert